EPM3256AFC256-10 vs EPM3512AFC-7N 比較
詳細並排比較 EPM3256AFC256-10 由 Altera 與 EPM3512AFC-7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ 最後購買機會Intel
EPM3512AFC-7N - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel (Altera)
EPM3512AFC-7N ✓ 啟用中規格比較
| 參數 | EPM3256AFC256-10 | EPM3512AFC-7N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | CMOS, EEPROM-based |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 (16 macrocells each) | 16 |
| Maximum User I/Os | 161 | — |
| Propagation Delay (tPD) | 10 ns | 7.5 ns (speed grade -7) |
| Internal Counter Frequency (fCNT) | 95.2 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant | — |
| In-System Programmability | Yes (3.3 V ISP via JTAG IEEE 1149.1) | Yes - IEEE Std. 1532 / JTAG (IEEE 1149.1) |
| 工作溫度 | 0°C to +70°C (Commercial) | 0 C to +70 C (commercial) |
| 封裝 | 256-ball FBGA (Fine-Line BGA) | BGA-256 (FineLine BGA) |
| Pitch | [DATA_NEEDED: BGA ball pitch] | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Macrocells | — | 512 |
| User I/Os | — | 208 |
| Dedicated Inputs | — | 16 |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Programming Interface | — | JTAG (4-wire TCK/TMS/TDI/TDO) |