EPM3256AQC208-10 vs EPM3512AQC208-10 比較
詳細並排比較 EPM3256AQC208-10 由 Altera 與 EPM3512AQC208-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 Obsolete規格比較
| 參數 | EPM3256AQC208-10 | EPM3512AQC208-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | — |
| Macrocells | 256 | 512 |
| Usable Gates | 5,000 | 10,000 |
| User I/Os | 161 | 208 |
| 腳位數 | 208 | — |
| 封裝 | 208-BFQFP (PQFP, Gull Wing) | 208-pin PQFP |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Tolerance | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| 工作溫度 | 0 °C to +70 °C (Commercial) | 0C to +70 C (commercial) |
| PCI-SIG Compliance | Yes (speed grades -4, -5, -6, -7, -10) | — |
| Global Clock Networks | 4 (CLK, CLR, OE, GCLK) | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in verified data] |
| Logic Array Blocks (LABs) | — | 32 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |