EPM3256AQC208-7N vs EPM3256AQC208-10N 比較

詳細並排比較 EPM3256AQC208-7N 由 Intel 與 EPM3256AQC208-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3256AQC208-7N EPM3256AQC208-10N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 Obsolete
Family MAX 3000A —
Device Type CPLD - Complex Programmable Logic Device —
Macro Cells 256 —
User I/Os 161 —
Logic Gates (Usable) 5,000 —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency 126.6 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Supply Voltage VCCIO 3.3 V or 2.5 V (MultiVolt) —
Programming Technology EEPROM (non-volatile) —
In-System Programmability Yes, IEEE Std. 1532 compliant —
JTAG Boundary Scan Yes —
工作溫度 0 C to +70 C (Commercial) 0C to +70C (Commercial)
封裝 208-pin PQFP —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Series — MAX 3000A
Programmable Type — In-System Programmable (EEPROM)
Number of Macrocells — 256
Number of Logic Elements/Blocks — 16 LABs
Usable Gates — 10,000
Number of I/O Pins — 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) — 10 ns (max)
Maximum Counter Frequency — 227.3 MHz
Supply Voltage - Internal — 3.0 V to 3.6 V (3.3 V typical)
封裝 / 外殼 — 208-BFQFP / 208-PQFP (28x28 mm)
ISP Compliance — IEEE Std. 1532
Boundary Scan — IEEE Std. 1149.1 (JTAG)
I/O Tolerance — 5 V tolerant, MultiVolt interface

資料表與資源

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