EPM3256ATC144-10 vs EPM3512ATC144 比較
詳細並排比較 EPM3256ATC144-10 由 Intel 與 EPM3512ATC144 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 Obsolete規格比較
| 參數 | EPM3256ATC144-10 | EPM3512ATC144 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Manufacturer | Intel (formerly Altera) | — |
| Series | MAX 3000A | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Programmable Type | In-System Programmable (EEPROM-based, IEEE 1532) | — |
| Macrocells | 256 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 5,000 | — |
| Number of I/O Pins | 116 | — |
| Propagation Delay (tpd max) | 10 ns | — |
| Counter Frequency (max) | 95.2 MHz | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Logic Level Support | MultiVolt - 5.0 V, 3.3 V, 2.5 V | — |
| 工作溫度 | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| 封裝 | 144-pin TQFP (20x20 mm) | TQFP-144 (20x20 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | — |
| Process Technology | CMOS EEPROM | — |
| RoHS 狀態 | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free | Compliant (lead-free suffix variants available) |
| Family | — | MAX 3000A |
| Maximum User I/O Pins | — | 212 |
| Core Supply Voltage | — | 3.3 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 (4-pin) |
| Maximum Frequency | — | 116 MHz |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns] |
| Product Terms per Macrocell | — | 32 (expandable) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant |
| MSL 等級 | — | 3 |