EPM3256ATC144-10AA vs EPM3256ATC144-10N 比較

詳細並排比較 EPM3256ATC144-10AA 由 Altera 與 EPM3256ATC144-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM3256ATC144-10N EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera

EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera

EPM3256ATC144-10N ⚠ 最後購買機會

規格比較

參數 EPM3256ATC144-10AA EPM3256ATC144-10N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Family MAX 3000A —
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macrocells 256 —
Usable Gates 5,000 5,000 (up to 10,000 usable in family)
Propagation Delay (tPD) 10 ns 10 ns
User I/O Pins 116 —
Maximum Operating Frequency 95.2 MHz —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V —
Technology CMOS, EEPROM-based configuration —
封裝 144-pin TQFP 144-LQFP (TQFP, ATC suffix)
安裝類型 Surface Mount Surface Mount
工作溫度 0C to +70C (Commercial) 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix]
In-System Programming IEEE Std. 1532 compliant —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data]
Series — MAX 3000A
Macro Cells — 256
Number of I/Os — 116
Number of Logic Elements / Blocks — 16 LABs
Supply Voltage (VCCINT) — 3.3 V
Maximum Counter Frequency — 227.3 MHz
Global Clocks — 3
Global Clear / OE — Yes (1 global clear, 1 global OE)
Program Memory Type — EEPROM (non-volatile, in-system programmable)
JTAG Support — IEEE Std. 1149.1 with pin-locking
ISP Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
Lead-Free / Halogen-Free — [DATA_NEEDED: not explicitly confirmed in verified data]

資料表與資源

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