EPM3256ATC144-7 vs EPM3256ATC144-10 比較
詳細並排比較 EPM3256ATC144-7 由 Altera 與 EPM3256ATC144-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 Obsolete規格比較
| 參數 | EPM3256ATC144-7 | EPM3256ATC144-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 3000A | — |
| Macrocells | 256 | 256 |
| User I/Os | 116 | — |
| Logic Elements / Gates | 600 to 10,000 usable gates | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Speed Grade | -7 | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| In-System Programming | IEEE Std. 1532 compliant, 3.3 V ISP | — |
| 封裝 | TQFP-144 (LFQFP, gull-wing) | 144-pin TQFP (20x20 mm) |
| 工作溫度 | 0C to +70C (Commercial) | 0 C to +70 C (Commercial) |
| 腳位數 | 144 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) | — |
| JTAG Support | IEEE Std. 1149.1 boundary-scan | — |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | MAX 3000A |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Programmable Type | — | In-System Programmable (EEPROM-based, IEEE 1532) |
| Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | 5,000 |
| Number of I/O Pins | — | 116 |
| Propagation Delay (tpd max) | — | 10 ns |
| Counter Frequency (max) | — | 95.2 MHz |
| Core Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Logic Level Support | — | MultiVolt - 5.0 V, 3.3 V, 2.5 V |
| JTAG / Boundary Scan | — | Yes (IEEE 1149.1) |
| Process Technology | — | CMOS EEPROM |
| RoHS 狀態 | — | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free |