EPM5016DC-15 vs EPM5016DC-17 比較
詳細並排比較 EPM5016DC-15 由 Altera 與 EPM5016DC-17 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-15 | EPM5016DC-17 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 2 | — |
| Dedicated Inputs | 4 | — |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Programming Voltage (VPP) | 12.75 V | — |
| 工作溫度 | 0 °C to 70 °C (commercial) | 0C to +70C (commercial) |
| 封裝 | Ceramic DIP-24 (windowed) | Ceramic DIP-24 (DC suffix) |
| 安裝類型 | Through-Hole | Through-hole |
| Process Technology | CMOS EPROM | 0.75 micron CMOS EEPROM |
| Configuration Memory | Non-volatile UV-erasable EPROM | On-chip EEPROM (non-volatile) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | [DATA_NEEDED: confirmed compliance status from manufacturer] |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Logic Elements | — | [DATA_NEEDED: LE count for MAX 5000 family] |
| User I/O Pins (max) | — | 24 |
| Propagation Delay (tPD) | — | 17 ns |
| Counter Frequency (fCNT) | — | 67 MHz |
| I/O Standard | — | TTL-compatible |
| 腳位數 | — | 24 |
| In-System Programmability | — | Yes (ByteBlaster / BitBlaster) |