EPM5016DC-15 vs EPM5016DI-20 比較
詳細並排比較 EPM5016DC-15 由 Altera 與 EPM5016DI-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-15 | EPM5016DI-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 2 | — |
| Dedicated Inputs | 4 | 7 |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 12.75 V | — |
| 工作溫度 | 0 °C to 70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | Ceramic DIP-24 (windowed) | 20-pin Ceramic DIP (DI), windowed |
| 安裝類型 | Through-Hole | — |
| Process Technology | CMOS EPROM | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | [DATA_NEEDED: RoHS compliance] |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (UV-erasable CMOS) |
| Propagation Delay (tPD) | — | 20 ns |
| 最大時脈頻率 | — | 62.5 MHz |
| Total Inputs | — | 16 |
| Configurable I/O Pins | — | 8 |
| External Clock Inputs | — | 1 |
| Product Terms per Output | — | 8 |
| Output Functions per Macrocell | — | 8 |
| Technology | — | CMOS EPROM |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| Speed Grade | — | -20 (20 ns tPD) |
| 供應電壓 | — | [DATA_NEEDED: VCC nominal] |