EPM5032DC-15 vs EPM5032DC-20 比較
詳細並排比較 EPM5032DC-15 由 Altera 與 EPM5032DC-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete
規格比較
| 參數 | EPM5032DC-15 | EPM5032DC-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable EPLD (PAL-type CMOS) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 600 | 600 |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V |
| Logic Family | CMOS, TTL-compatible I/O | — |
| Programmable Pins | 16 bidirectional I/O + 4 dedicated input = 20 | — |
| Total Package Pins | 28 | — |
| 封裝 | CERDIP-28 (windowed, through-hole) | 20-pin DIP (Windowed Ceramic, 0.3" wide) |
| 安裝類型 | Through-Hole (DIP) | Through-Hole |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Erasure Method | UV light through ceramic quartz window | — |
| Process Technology | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (per IC-Components listing) |
| Lead-Free | unknown | — |
| Product Family | — | MAX 5000 |
| Programmable Technology | — | UV-Erasable / OTP EPROM |
| Maximum Frequency (fCNT) | — | 71.4 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Logic Blocks | — | 4 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: I/O pin count for DIP-20 variant] |
| Lead Free | — | [DATA_NEEDED: confirmed lead-free] |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Programming Method | — | Altera MAX+PLUS II / Quartus (legacy support) |