EPM5032DC-2 vs EPM5032DC-25 比較

詳細並排比較 EPM5032DC-2 由 Altera 與 EPM5032DC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5032DC-2 EPM5032DC-25
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Product Type CPLD (Complex Programmable Logic Device) —
Series MAX 5000 —
Macrocells 32 32
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 —
封裝 20-pin CDIP (Ceramic DIP) CDIP-28 (Windowed Ceramic DIP-28)
Speed Grade -2 (tPD ~25 ns, commercial) —
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) —
Supply Voltage (VCC) 5 V (single supply, +/-5%) —
工作溫度 0C to +70C (commercial grade) [DATA_NEEDED: operating temperature range]
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
RoHS 狀態 [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] Lead Free / RoHS Compliant (per distributor listings)
安裝類型 Through-Hole (DIP) —
MSL 等級 Not applicable (through-hole hermetic ceramic) —
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (EPLD)
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Architecture — PAL-Type, Single-LAB, 32-Macrocell
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

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