EPM5032DC-20 vs EPM5032DC 比較
詳細並排比較 EPM5032DC-20 由 Intel 與 EPM5032DC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DC-20 | EPM5032DC |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Programmable Technology | UV-Erasable / OTP EPROM | — |
| Usable Gates | 600 | — |
| Macrocells | 32 | 32 |
| Maximum Frequency (fCNT) | 71.4 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | DC (commercial) |
| Supply Voltage (VCC) | 5 V | — |
| 封裝 | 20-pin DIP (Windowed Ceramic, 0.3" wide) | DIP-24 (ceramic, windowed) |
| 安裝類型 | Through-Hole | Through-hole (DIP) |
| Logic Blocks | 4 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: I/O pin count for DIP-20 variant] | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C |
| RoHS 狀態 | Compliant (per IC-Components listing) | [DATA_NEEDED: RoHS status] |
| Lead Free | [DATA_NEEDED: confirmed lead-free] | — |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | — |
| Programming Method | Altera MAX+PLUS II / Quartus (legacy support) | — |
| Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 1 |
| Technology | — | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| Configuration Memory | — | EPROM (UV-erasable via package window) |
| 腳位數 | — | 24 |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| 生命週期狀態 | — | Obsolete (mature legacy) |