EPM5032DC-20 vs EPM5032DM 比較
詳細並排比較 EPM5032DC-20 由 Intel 與 EPM5032DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DC-20 | EPM5032DM |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Technology | UV-Erasable / OTP EPROM | — |
| Usable Gates | 600 | 600 to 1000 (typical) |
| Macrocells | 32 | 32 |
| Maximum Frequency (fCNT) | 71.4 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| 封裝 | 20-pin DIP (Windowed Ceramic, 0.3" wide) | CDIP-28 (ceramic windowed DIP, 28-pin) |
| 安裝類型 | Through-Hole | Through-hole (DIP) |
| Logic Blocks | 4 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: I/O pin count for DIP-20 variant] | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | -55C to +125C (military/extended, ceramic package) |
| RoHS 狀態 | Compliant (per IC-Components listing) | Non-compliant (ceramic DIP with UV window) |
| Lead Free | [DATA_NEEDED: confirmed lead-free] | — |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | — |
| Programming Method | Altera MAX+PLUS II / Quartus (legacy support) | — |
| Device Family | — | MAX 5000 |
| Propagation Delay (tPD) | — | 25 ns |
| Logic Inputs | — | 32 |
| Process Technology | — | CMOS EEPROM |
| Standby Current | — | [DATA_NEEDED: ICC standby current] |
| Programming Technology | — | UV-erasable (windowed) EEPROM |
| Logic Function | — | Combinational and registered (synchronous) |
| Output Polarity | — | Programmable |
| Program Retention | — | Non-volatile (EEPROM) |
| Lead-Free | — | No (ceramic DIP contains lead) |