EPM5032DI-20 vs EPM5032DC 比較
詳細並排比較 EPM5032DI-20 由 Intel 與 EPM5032DC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DI-20 | EPM5032DC |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Altera legacy EPLD) | MAX 5000 |
| Architecture | CMOS PAL-type EPLD with PIA | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| 最大時脈頻率 | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| 封裝 | Ceramic DIP-20 (windowed, UV-erasable) | DIP-24 (ceramic, windowed) |
| 工作溫度 | Industrial (per 'I' suffix) | 0C to +70C |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 1 |
| Speed Grade | — | DC (commercial) |
| Technology | — | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| Configuration Memory | — | EPROM (UV-erasable via package window) |
| 安裝類型 | — | Through-hole (DIP) |
| 腳位數 | — | 24 |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| 生命週期狀態 | — | Obsolete (mature legacy) |