EPM5032DI-25 vs EPM5032SC-25 比較
詳細並排比較 EPM5032DI-25 由 Altera 與 EPM5032SC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DI-25 | EPM5032SC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable Programmable Logic Device (PLD) | EPLD (Erasable/OTP Programmable Logic Device) |
| Architecture | PAL-type, CMOS, AND-OR sum-of-products | — |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Logic Gates | [DATA_NEEDED: equivalent gate count] | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Registered Outputs | 16 | — |
| Global Clocks | 1 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| 供應電壓 | 5 V | — |
| Process Technology | CMOS | — |
| 封裝 | Ceramic DIP, windowed (UV-erasable) | PDSO-28 (Plastic DIP Small Outline, SOIC-28 equivalent) |
| 腳位數 | [DATA_NEEDED: exact pin count - 24 or 28] | — |
| 工作溫度 | 0C to +70C (commercial) | — |
| I/O Standard | TTL-compatible | — |
| Programmability | UV-erasable, EPROM-based | — |
| Development Tool | MAX+PLUS II / A+PLUS | — |
| RoHS 狀態 | [DATA_NEEDED: likely non-compliant due to ceramic DIP] | [DATA_NEEDED: RoHS status - legacy Altera part; verify with distributor] |
| Lifecycle | Not Recommended for New Designs (NRND) | — |
| Bidirectional I/O | — | 16 |
| Total Pin Count | — | 28 |
| Speed Grade | — | -25 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | 91 MHz |
| Supply Voltage (VCC) | — | 5 V (typical, 4.5 V to 5.5 V) |
| Technology | — | CMOS, UV-erasable or OTP |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Operating Temperature (Commercial) | — | 0C to +70C |
| 安裝類型 | — | Surface Mount |
| Programming Method | — | Altera programming hardware (legacy iMPACT or MAX+PLUS II) |