EPM5032DM883B vs EPM5032DM 比較
詳細並排比較 EPM5032DM883B 由 Altera 與 EPM5032DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DM883B | EPM5032DM |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Classic EPLD) | — |
| Macrocells | 32 | 32 |
| Logic Elements | 32 macrocells (MAX architecture) | — |
| Technology | UV-erasable EPROM cell | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | 25 ns |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL-compatible I/O) | 5 V (typical) |
| 工作溫度 | MILITARY (per /883B screen) | -55C to +125C (military/extended, ceramic package) |
| MIL-STD-883 Screening | Class B (DM/883B) | — |
| Package Type | WDIP-28 (ceramic DIP with quartz window) | — |
| 腳位數 | 28 | — |
| 安裝類型 | Through-Hole | Through-hole (DIP) |
| Terminal Form | Through-Hole | — |
| Package Shape | RECTANGULAR | — |
| Programming Method | Programmer + UV erase | — |
| RoHS 狀態 | [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] | Non-compliant (ceramic DIP with UV window) |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 600 to 1000 (typical) |
| Logic Inputs | — | 32 |
| Process Technology | — | CMOS EEPROM |
| 封裝 | — | CDIP-28 (ceramic windowed DIP, 28-pin) |
| Standby Current | — | [DATA_NEEDED: ICC standby current] |
| Programming Technology | — | UV-erasable (windowed) EEPROM |
| Logic Function | — | Combinational and registered (synchronous) |
| Output Polarity | — | Programmable |
| Program Retention | — | Non-volatile (EEPROM) |
| Lead-Free | — | No (ceramic DIP contains lead) |