EPM5032JC-20 vs EPM5032SC-20 比較
詳細並排比較 EPM5032JC-20 由 Altera 與 EPM5032SC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032JC-20 | EPM5032SC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| 最大時脈頻率 | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 7 |
| Total Inputs | 24 | — |
| 封裝 | 68-pin JLCC (windowed ceramic) | 20-pin SOIC (Small Outline) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-type, CMOS, UV-erasable |
| 生命週期狀態 | Obsolete (legacy Altera MAX 5000) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| I/O Pins | — | 16 |
| Outputs | — | 16 |
| Speed Grade | — | -20 (20 ns) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| 工作溫度 | — | 0 °C to +70 °C (commercial grade) |
| 安裝類型 | — | Surface Mount |
| 供應電壓 | — | [DATA_NEEDED: VCC typical range] |
| Technology | — | CMOS EPROM cell |
| Programmability | — | One-time programmable (windowless SOIC) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status not confirmed in verified data] |