EPM5032SC-25 vs EPM5032LC-20 比較
詳細並排比較 EPM5032SC-25 由 Intel 與 EPM5032LC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032SC-25 | EPM5032LC-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable/OTP Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O | 16 | — |
| Total Pin Count | 28 | — |
| 封裝 | PDSO-28 (Plastic DIP Small Outline, SOIC-28 equivalent) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Speed Grade | -25 | -20 (20 ns pin-to-pin) |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Counter Frequency (fCNT) | 91 MHz | — |
| Supply Voltage (VCC) | 5 V (typical, 4.5 V to 5.5 V) | 5 V ±5% |
| Technology | CMOS, UV-erasable or OTP | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy Altera part; verify with distributor] | [DATA_NEEDED: RoHS status] |
| Programming Method | Altera programming hardware (legacy iMPACT or MAX+PLUS II) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Usable Gates | — | 600 gates |
| Logic Blocks (LABs) | — | 1 |
| Maximum Frequency | — | 71.4 MHz |
| Propagation Delay (tPD) | — | 20 ns |
| 工作溫度 | — | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Bidirectional I/O Pins | — | 16 |
| Total Inputs | — | 24 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| MSL 等級 | — | [DATA_NEEDED: MSL] |