EPM5128GC-1 vs EPM5064LC-1 比較
詳細並排比較 EPM5128GC-1 由 Altera 與 EPM5064LC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128GC-1 | EPM5064LC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | — |
| Macrocells | 128 | 64 |
| Usable Gates | 2,500 | 1.25K (approx.) |
| Dedicated Inputs | 7 | 7 |
| Maximum User I/O Pins | 52 | — |
| Nominal Supply Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | 40 ns |
| 封裝 | PGA-96+ (Pin Grid Array, ceramic windowed) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Technology | CMOS, UV-erasable EPROM | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | — |
| Security Bit | Programmable, prevents readback | — |
| Programming Method | UV erase + EPROM program (or device programmer) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Internal Operating Frequency | — | 62.5 MHz |
| Input Lines | — | 36 |
| Output Lines | — | 28 |
| Programming Technology | — | OTP / UV-Erasable EPROM |
| Process Technology | — | CMOS |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |