EPM5192AGC vs EPM5192GC-1 比較
詳細並排比較 EPM5192AGC 由 Altera 與 EPM5192GC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AGC | EPM5192GC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 (Classic) |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | CMOS, UV-erasable / OTP |
| 封裝 | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | 100-pin Ceramic PGA (GC) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| 供應電壓 | [DATA_NEEDED: VCC nominal and tolerance] | — |
| 安裝類型 | Through-hole (Pin Grid Array) | Through-Hole (PGA) |
| RoHS 狀態 | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Configuration Method | — | UV-Erase / One-Time Programmable |
| Interconnect | — | Peripheral Interconnect Array (PIA) |