EPM5192AJC84-15 vs EPM5192ALC84-20 比較
詳細並排比較 EPM5192AJC84-15 由 Altera 與 EPM5192ALC84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete規格比較
| 參數 | EPM5192AJC84-15 | EPM5192ALC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable/OTP Complex PLD (EPLD) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket-compatible) |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programming Method | UV-erase + EPROM programming (windowed package) | UV-erase + EPROM (One-Time-Programmable option) |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS 狀態 | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS status not in provided web data] |
| Process Technology | CMOS EPROM | CMOS |
| Series | — | Altera MAX 5000 |
| Speed Grade | — | -20 (20 ns pin-to-pin delay) |
| Terminal Pitch | — | 1.270 mm |
| Terminal Form | — | J-bend |
| Package Code | — | QCCJ (PLCC-84) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Logic Family | — | MAX 5000 EPLD |
| I/O Compatibility | — | TTL-compatible |
| Configuration Memory | — | EPROM (UV-erasable) |