EPM5192AJM84-15 vs EPM5192AJM84-20 比較
詳細並排比較 EPM5192AJM84-15 由 Altera 與 EPM5192AJM84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AJM84-15 | EPM5192AJM84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | CMOS UV-Erasable/OTP Complex PLD |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 84 | 64 |
| Speed Grade | -15 (15 ns tPD) | — |
| Propagation Delay (tPD) | 15 ns | 33 ns (speed grade -20) |
| Maximum Operating Frequency | 83.3 MHz | — |
| Process Technology | 5 V CMOS, UV-EPROM | CMOS EPROM (UV-erasable) |
| 封裝 | 84-pin ceramic J-lead (JM84) | 84-pin CQFP (S-CQCC-J84, J-lead) |
| 安裝類型 | Surface Mount (ceramic J-lead) | — |
| 工作溫度範圍 | -55C to +125C (military grade) | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| Erase Method | Ultraviolet (windowed ceramic package) | — |
| Programming Method | EPROM-style (programmer + UV erase) | — |
| I/O Standard | TTL-compatible CMOS | — |
| Development Tool | Altera MAX+PLUS II | — |
| RoHS 狀態 | Non-compliant (ceramic with UV window) | [DATA_NEEDED: rohs status] |
| 生命週期狀態 | Obsolete (EOL by Altera, now supported by Microchip / 3rd-party distributors) | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | MAX 5000 (EPM5192) |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| 最大時脈頻率 | — | 66.7 MHz |
| Terminal Form | — | J-Bend |
| Temperature Grade | — | MILITARY |
| Erasure Method | — | UV (quartz-windowed CQFP) or OTP |