EPM5192ALM84-15 vs EPM5192AJI84-15 比較
詳細並排比較 EPM5192ALM84-15 由 Altera 與 EPM5192AJI84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192ALM84-15 | EPM5192AJI84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | OTP Complex Programmable Logic Device (CPLD) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 15 ns (per '-15' speed grade suffix) | 15 ns |
| Propagation Delay (vendor-stated) | 25 ns (per MicrochipUSA listing) | — |
| Maximum Internal Frequency | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 4.5 V to 5.5 V (nominal 5 V) |
| Technology | CMOS | — |
| Programmability | Windowless, OTP (One-Time Programmable) | — |
| Package Type | PLCC-84 (QCCJ, J-bend, square) | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window |
| Number of Terminals | 84 | — |
| Terminal Form | J BEND | — |
| Temperature Grade | MILITARY | — |
| 安裝類型 | Surface Mount / Socket (PLCC) | Through-Hole (SMD socket-compatible) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | unknown |
| 工作溫度範圍 | [DATA_NEEDED: exact military temp range] | — |
| Device Family | — | MAX 5000 EPLD |
| Product Type | — | UV-Erasable / OTP Complex PLD |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 84 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| 工作溫度 | — | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Programming Method | — | UV erase + EPROM program via standard Altera programmer |
| Design Tool Support | — | MAX+PLUS II (legacy); not supported by modern Quartus Prime |
| Lead-Free | — | unknown |
| 無鹵素 | — | unknown |
| Functional Equivalent (Plastic OTP) | — | EPM5192AJC84-15 (windowless plastic JLCC, same die) |