EPM5192GC-1 vs EPM5192GC-2 比較
詳細並排比較 EPM5192GC-1 由 Altera 與 EPM5192GC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GC-1 | EPM5192GC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Classic) | MAX 5000 |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封裝 | 100-pin Ceramic PGA (GC) | — |
| 安裝類型 | Through-Hole (PGA) | Through-hole (PGA socket) |
| Configuration Method | UV-Erase / One-Time Programmable | — |
| Interconnect | Peripheral Interconnect Array (PIA) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | Commercial (0C to +70C) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Propagation Delay (tPD) | — | 12 ns typical (-2 grade) |
| Counter Frequency | — | 100 MHz minimum |
| Technology | — | CMOS EPROM |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Speed Grade | — | -2 |