EPM5192GC-2 vs EPM5192GC1 比較
詳細並排比較 EPM5192GC-2 由 Altera 與 EPM5192GC1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GC-2 | EPM5192GC1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | — |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | — |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | — |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | — |
| Counter Frequency | 100 MHz minimum | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V |
| Technology | CMOS EPROM | — |
| Programmable Technology | UV-erasable / one-time programmable | — |
| Programming Toolchain | Altera MAX+PLUS II | — |
| Package Type | Pin Grid Array (PGA), ceramic | Ceramic PGA (Pin Grid Array) |
| 工作溫度 | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | -2 | — |
| RoHS 狀態 | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | unknown |
| 安裝類型 | Through-hole (PGA socket) | Through-hole (PGA) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Process Technology | — | EPROM-based CMOS |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| 腳位數 | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |