EPM5192IC-1 vs EPM5192JC-1 比較

詳細並排比較 EPM5192IC-1 由 Altera 與 EPM5192JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5192IC-1 EPM5192JC-1
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 5000 EPLD MAX 5000
Macrocells 192 192
Usable Gates 3750 3750
Dedicated Inputs 7 —
I/O Pins 64 —
Pin-to-Pin Delay (tPD) 15 ns (max, -1 speed grade) —
Counter Frequency (fCNT) 76.9 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (nominal 5 V) 4.75 V to 5.25 V
工作溫度 -40C to +85C (industrial) 0 C to +70 C (commercial)
Technology CMOS, UV-erasable, in-system programmable CMOS, UV-Erasable / OTP
封裝 68-pin ceramic J-lead (IC-1 suffix) —
Programming Interface JTAG / IEEE Std 1149.1 boundary scan Altera MAX programming interface (parallel, pre-JTAG for this family)
Security Bit Yes (design protection) —
Supply Current (Icc, typical) [DATA_NEEDED: Icc] mA —
Output Drive Current (IOH/IOL) [DATA_NEEDED: IOH/IOL] mA —
Device Type — CPLD - Complex Programmable Logic Device
Propagation Delay (tPD) — 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) — 62.5 MHz
User I/O Pins — 84
Package Type — 84-pin Ceramic Quad Flat Pack (CQFP), windowed
JEDEC Package Code — S-CQCC-J84
Configuration Memory — UV-EPROM (erasable under UV lamp)
Process — CMOS EPROM
I/O Standard — TTL/CMOS 5 V compatible

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