EPM5192JC-1N vs EPM5192GM883B-2 比較
詳細並排比較 EPM5192JC-1N 由 Altera 與 EPM5192GM883B-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC-1N | EPM5192GM883B-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device), UV-erasable |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates | 3750 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs (GCLK) | 1 | — |
| Propagation Delay (tPD) | 40 ns | 45 ns (-2 speed grade) |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS EPROM (UV-erasable) | 5 V CMOS |
| 封裝 | 84-pin Ceramic Quad Flat Pack (CQFP) | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 |
| JEDEC Package Code | S-CQCC-J84 | S-CPGA-P84 |
| 工作溫度 | [DATA_NEEDED: industrial/commercial temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming Interface | JTAG / Altera ByteBlaster | — |
| Maximum Internal Clock Frequency | — | 33.3 MHz |
| Supply Voltage (VCC, nominal) | — | 5 V |
| Package Outline | — | 28.45 mm square (approx.) |
| Military Screening | — | MIL-STD-883 (per '883' suffix) |
| 安裝類型 | — | Through-hole PGA socket |
| RoHS 狀態 | — | non_compliant (ceramic CPGA with MIL-STD-883 screening) |