EPM5192JI-1 vs EPM5192JC-1 比較
詳細並排比較 EPM5192JI-1 由 Intel 與 EPM5192JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JI-1 | EPM5192JC-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | 84 |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tPD) | 55 ns | 40 ns (speed grade -1) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 4.75 V to 5.25 V |
| Process Technology | CMOS EPROM | — |
| 封裝 | 84-pin JLCC (Windowed ceramic J-lead) | — |
| 工作溫度 | Industrial, -40 C to +85 C | 0 C to +70 C (commercial) |
| Configuration Memory | UV-erasable EPROM | UV-EPROM (erasable under UV lamp) |
| Programming Method | External EPROM programmer (via programming hardware) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | — |
| Speed Grade | -1 (slowest grade in EPM5192 family) | — |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array | — |
| Technology | — | CMOS, UV-Erasable / OTP |
| Usable Gates | — | 3750 |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |