EPM5192LC-1 vs EPM5192GC-2 比較
詳細並排比較 EPM5192LC-1 由 Altera 與 EPM5192GC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-1 | EPM5192GC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| 腳位數 | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | Pin Grid Array (PGA), ceramic |
| Propagation Delay | 25 ns | — |
| 最大時脈頻率 | 50 MHz | — |
| 供應電壓 | 5 V nominal (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable / OTP EPROM cell | CMOS EPROM |
| 工作溫度 | 0C to +70C (commercial) | Commercial (0C to +70C) |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | -2 |
| RoHS 狀態 | Non-compliant (ceramic LDCC with Pb-bearing terminations) | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Propagation Delay (tPD) | — | 12 ns typical (-2 grade) |
| Counter Frequency | — | 100 MHz minimum |
| Supply Voltage (VCC) | — | 5 V nominal |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| 安裝類型 | — | Through-hole (PGA socket) |