EPM5192LC84-2 vs EPM5192LI 比較
詳細並排比較 EPM5192LC84-2 由 Altera 與 EPM5192LI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC84-2 | EPM5192LI |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| 封裝 | 84-pin PLCC (LC) | 84-pin PQCC (J84) |
| Speed Grade | -2 | — |
| 供應電壓 | 5 V (TTL-compatible I/O) | — |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable EPROM |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| 工作溫度 | Commercial (0C to +70C) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Non-compliant (SnPb lead finish typical for this vintage) | unknown |
| 生命週期狀態 | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 12 |
| Maximum Operating Frequency | — | 40 MHz |
| Propagation Delay (tPD) | — | 55 ns |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 72 |
| User I/O Pins | — | 64 |
| JEDEC Package Code | — | S-PQCC-J84 |
| 工作溫度範圍 | — | Industrial (-40C to +85C) |