EPM5192LI-2 vs EPM5192LI 比較
詳細並排比較 EPM5192LI-2 由 Altera 與 EPM5192LI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LI-2 | EPM5192LI |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable/OTP Complex PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O | 64 | — |
| Total Inputs | 72 (7 dedicated + 64 I/O) | 72 |
| Propagation Delay (tpd) | 55 ns (max) | — |
| Maximum Internal Frequency | 100 MHz | — |
| 供應電壓 | 4.5 V to 5.5 V | — |
| 工作溫度 | -40 C to +85 C (industrial) | — |
| Typical Power Dissipation | 600 mW at 5 V / 25 C | — |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable EPROM |
| 封裝 | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 | 84-pin PQCC (J84) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| Design Toolchain | Altera MAX+plus II | — |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 40 MHz |
| Propagation Delay (tPD) | — | 55 ns |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| JEDEC Package Code | — | S-PQCC-J84 |
| 工作溫度範圍 | — | Industrial (-40C to +85C) |