EPM570F100I5N vs EPM570F100A5N 比較
詳細並排比較 EPM570F100I5N 由 Altera 與 EPM570F100A5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570F100I5N | EPM570F100A5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Flash-based) | — |
| Logic Elements (LEs) | 570 | — |
| Macrocells | 440 | 440 |
| Maximum User I/Os | 76 | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 304 MHz | 201.1 MHz |
| Propagation Delay (tPD) | 8.7 ns (max), 5.4 ns (typical) | — |
| Supply Voltage (VCCINT) | 2.375 V to 3.6 V | — |
| Typical Supply Current (ICC) | 55 mA | — |
| I/O Standards Supported | LVCMOS, LVTTL, LVDS, SSTL, HSTL (1.5/1.8/2.5/3.3 V) | — |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | JTAG (IEEE 1149.1) / ISP |
| Global Clocks | 4 | — |
| 工作溫度 | -40C to +100C (Industrial) | 0°C to +85°C (commercial) |
| 封裝 | 100-ball FineLine BGA (11x11 mm) | 100-ball FBGA |
| 安裝類型 | Surface Mount | — |
| Process Technology | CMOS, Flash configuration cell | 0.18 µm flash |
| Hot Socketing | Supported | — |
| RoHS 狀態 | Compliant | Compliant |
| Logic Elements | — | 570 |
| Pin-to-Pin Delay (tPD) | — | 5.4 ns |
| User I/O Pins (max) | — | 76 |
| Global Clock Lines | — | 4 |
| Supply Voltage - Core | — | 3.3 V |
| Supply Voltage - I/O Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |