EPM570GF100C5N vs EPM570F100C5N 比較
詳細並排比較 EPM570GF100C5N 由 Altera 與 EPM570F100C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570GF100C5N | EPM570F100C5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Device Family | MAX II | — |
| Logic Elements | 570 | 570 |
| Macrocells | 440 | — |
| User I/Os | 76 | 76 |
| Propagation Delay (tPD) | 5.4 ns | 5.4 ns |
| 封裝 | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch | — |
| Configuration Memory | On-chip Flash (non-volatile) | On-chip Flash (instant-on, non-volatile) |
| Core Voltage | 1.8 V (internal) | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (5.0 V tolerant inputs) | — |
| 工作溫度 | -40C to +125C (industrial) | 0C to 85C (TJ) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1532 / JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) |
| RoHS 狀態 | Compliant (lead-free) | — |
| Logic Family / Process | CMOS, Flash-based LUT | — |
| LABs | 4 (16 macrocells per LAB) | — |
| Family | — | MAX II |
| Number of Macrocells | — | 440 |
| Number of Logic Array Blocks | — | 57 |
| Process Technology | — | 0.18 micron CMOS |
| Supply Voltage - Internal | — | 2.5 V, 3.3 V |
| I/O Standards Supported | — | 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| 封裝 / 外殼 | — | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch |
| Supplier Device Package | — | 100-FBGA |
| In-System Programmability | — | Yes (JTAG, IEEE 1532) |
| User Flash Memory (UFM) | — | 8 Kbit |
| Lead Free / RoHS | — | Yes (per verified data) |