EPM570GF256C3N vs EPM570GF256C4 比較

詳細並排比較 EPM570GF256C3N 由 Altera 與 EPM570GF256C4 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM570GF256C3N EPM570GF256C3N - 570 LEs MAX II G CPLD | Intel / Altera

EPM570GF256C3N - 570 LEs MAX II G CPLD | Intel / Altera

EPM570GF256C3N ✓ 啟用中

規格比較

參數 EPM570GF256C3N EPM570GF256C4
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II G MAX II
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements (LEs) 570 570
User I/Os 76 —
User Flash Memory 8 Kbit —
Logic Family CMOS —
Supply Voltage VCCINT 3.3 V (core) 1.71 V to 1.89 V (core, derived from 2.5/3.3 V)
I/O Bank Voltage 1.5 V / 1.8 V / 2.5 V / 3.3 V —
封裝 256-ball FineLine BGA (GF256), 17 x 17 mm, 1.0 mm pitch 256-ball FBGA (FineLine BGA)
安裝類型 Surface Mount (BGA) Surface Mount
工作溫度 -40C to +125C (industrial) 0 °C to +85 °C (commercial)
Programming Interface JTAG (IEEE 1149.1) / in-system programmable —
Configuration Memory On-chip Flash (non-volatile, instant-on) Non-volatile flash (instant-on, no boot PROM)
RoHS 狀態 Lead Free / RoHS Compliant Lead-free, RoHS compliant
Lead Free Yes —
Macrocells — 440
Maximum User I/Os — 212
Pin-to-Pin Delay (tPD) — 5.4 ns
I/O Bank Voltage VCCIO — 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage LVCMOS/LVTTL)
Ball Pitch — 1.0 mm
Process Technology — 0.18 µm CMOS, flash-based configuration
JTAG Support — IEEE 1149.1 boundary-scan + ISP

資料表與資源

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