EPM570GT100I5 vs EPM570GT100C5N 比較
詳細並排比較 EPM570GT100I5 由 Altera 與 EPM570GT100C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570GT100I5 | EPM570GT100C5N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | MAX II | MAX II |
| Logic Elements (LE) | 570 | — |
| Macrocells | 440 | — |
| Maximum User I/O Pins | 76 | — |
| Propagation Delay (tPD) | 5.4 ns (typ) | — |
| Internal Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| User I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| User Flash Memory | 8 Kbits | — |
| Programmability | In-System Programmable (ISP) via JTAG, non-volatile flash | Flash-based, non-volatile (ISP via JTAG) |
| Configuration Time | Instant-On (< 1 ms, no external PROM required) | — |
| 工作溫度 | -40 C to +100 C (Industrial, "I5") | 0C to +85C (Commercial) |
| 封裝 | 100-pin TQFP (14x14 mm, 0.5 mm pitch) | TQFP-100 |
| 安裝類型 | Surface Mount (Gull-wing leads) | Surface Mount |
| Typical Active Current | [DATA_NEEDED: typical active ICC] | — |
| Speed Grade | GT (fast) | — |
| RoHS 狀態 | Compliant | Compliant |
| JTAG Support | IEEE 1149.1 boundary scan | IEEE 1149.1 boundary scan |
| Global Clock Networks | 4 | — |
| Logic Elements | — | 570 |
| Equivalent Macrocells | — | 440 |
| User I/O | — | 76 |
| LABs | — | 36 |
| Maximum Frequency | — | 304 MHz |
| Pin-to-Pin Delay | — | [DATA_NEEDED: tPD value] |
| User Flash Memory (UFM) | — | 8 Kbit |
| Operating Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS |