EPM570T100C5N vs EPM240T100I3N 比較
詳細並排比較 EPM570T100C5N 由 Intel 與 EPM240T100I3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
EPM240T100I3N ⚠ 最後購買機會規格比較
| 參數 | EPM570T100C5N | EPM240T100I3N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Series | MAX II | — |
| Family | CPLD - MAX II | MAX II |
| Logic Elements (LE) | 570 | — |
| Macrocells | 440 | — |
| User I/Os | 76 | — |
| User Flash Memory | 8 Kbit | — |
| Process Technology | 0.18 µm 6-layer-metal Flash | — |
| Internal Performance | 201.1 MHz | 304 MHz |
| 供應電壓 | 2.5 V / 3.3 V | — |
| 工作溫度 | 0 °C to +85 °C (commercial) | — |
| 封裝 | 100-pin TQFP (T100) | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| 安裝類型 | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG / IEEE 1149.1 ISP |
| I/O Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt | — |
| RoHS 狀態 | Compliant | Compliant |
| Device Logic Elements / Macrocells | — | 192 macrocells |
| Maximum User I/O Pins | — | 80 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| On-chip User Flash Memory | — | 8 Kbits |
| Pin-to-pin Logic Delay (tPD1) | — | 4.6 ns |
| Global Clock Networks | — | 4 |
| Technology Node | — | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| MultiVolt I/O Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| 工作接面溫度 | — | -40C to +100C (industrial, 'I' grade) |
| Speed Grade | — | 3 |
| Instant-on (non-volatile) | — | Yes (flash-based) |
| MSL 等級 | — | 3 (per JEDEC J-STD-020) |