EPM570T100I5 vs EPM570GT100I5 比較

詳細並排比較 EPM570T100I5 由 Altera 與 EPM570GT100I5 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM570T100I5 EPM570GT100I5
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Series MAX II MAX II
Family EPM570 (MAX II) —
Logic Elements (LEs) 570 —
Equivalent Macrocells 440 —
User I/Os 76 —
Propagation Delay (tPD) 5.4 ns 5.4 ns (typ)
User Flash Memory (UFM) 8 Kbits —
Process Technology 0.18 micron, 6-layer-metal flash —
封裝 TQFP-100 (14x14x1 mm) 100-pin TQFP (14x14 mm, 0.5 mm pitch)
安裝類型 Surface Mount Surface Mount (Gull-wing leads)
工作溫度 -40C to +100C (industrial) -40 C to +100 C (Industrial, "I5")
Core Supply Voltage 3.0 V to 3.6 V —
I/O Standards Supported 1.5V / 1.8V / 2.5V / 3.3V LVCMOS/LVTTL —
Programming Interface JTAG (IEEE 1149.1), in-system programmable —
Configuration Method Non-volatile flash, instant-on —
RoHS 狀態 [DATA_NEEDED: RoHS compliance] Compliant
Logic Elements (LE) — 570
Macrocells — 440
Maximum User I/O Pins — 76
Internal Supply Voltage (VCCINT) — 1.71 V to 1.89 V
User I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
User Flash Memory — 8 Kbits
Programmability — In-System Programmable (ISP) via JTAG, non-volatile flash
Configuration Time — Instant-On (< 1 ms, no external PROM required)
Typical Active Current — [DATA_NEEDED: typical active ICC]
Speed Grade — GT (fast)
JTAG Support — IEEE 1149.1 boundary scan
Global Clock Networks — 4

資料表與資源

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