EPM570T100I5N vs EPM570T100C4 比較
詳細並排比較 EPM570T100I5N 由 Intel 與 EPM570T100C4 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570T100I5N | EPM570T100C4 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | MAX II | — |
| Family | EPM570 | MAX II |
| Logic Elements | 570 | — |
| Macrocells | 440 | 440 |
| User I/Os (max) | 76 | — |
| User Flash Memory | 8 Kbit | 8 Kbits |
| 封裝 | TQFP-100 (T100) | TQFP-100 (T100), 14 x 14 mm |
| 安裝類型 | Surface Mount | Surface Mount |
| Operating Supply Voltage (Core) | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) | — |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| In-System Programmable | Yes | — |
| Configuration Memory | Internal non-volatile Flash | — |
| Operating Temperature (Industrial) | -40C to +100C (junction) | — |
| RoHS 狀態 | Compliant | Compliant |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/O Pins (this package) | — | 80 |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.4 ns |
| General-Purpose SRAM | — | 4.4 Mbits |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| 工作溫度 | — | 0C to +85C (commercial) |
| Programming Interface | — | JTAG (IEEE 1149.1) - ISP |
| MSL 等級 | — | [DATA_NEEDED: MSL Level] |
| On-chip Oscillator | — | Yes (3.3 MHz / 5.5 MHz selectable) |
| Internal Logic Analyzers / ISP | — | JTAG-based in-system programmable, no external boot PROM required |