EPM570ZM256C7N vs EPM570F256C5N 比較
詳細並排比較 EPM570ZM256C7N 由 Altera 與 EPM570F256C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570ZM256C7N | EPM570F256C5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | MAX II Z | — |
| Family | MAX II | MAX II |
| Logic Elements (LE) | 570 | — |
| Macro Cells | 440 | — |
| User I/Os | 76 | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 123.5 MHz | 304 MHz |
| Pin-to-Pin Delay (tPD) | 5.0 ns | 5.4 ns |
| Core Supply Voltage | 1.71 V to 1.89 V (3.3 V with on-chip regulator) | — |
| I/O Supply Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS | 0.18 um |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0C to 85C (TJ) |
| 封裝 | 256-ball MBGA (Micro FBGA), 0.5 mm pitch, 6 × 6 mm | 256-FBGA (FineLine BGA) |
| Configuration Method | On-chip non-volatile (instant-on, ISP via JTAG) | — |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP | — |
| Lead-Free / RoHS | Lead-free / RoHS compliant | — |
| Logic Family | CMOS | — |
| Logic Elements | — | 570 |
| Number of Macrocells | — | 440 |
| Internal Supply Voltage | — | 2.5 V / 3.3 V |
| User I/O Count | — | 160 |
| Program Memory Type | — | Non-volatile Flash |
| MultiVolt I/O Support | — | 1.5V / 1.8V / 2.5V / 3.3V |
| Programming Interface | — | JTAG (IEEE 1149.1), in-system |
| 安裝類型 | — | Surface Mount |