EPM7096LC68-7 vs EPM7096LC68-15 比較
詳細並排比較 EPM7096LC68-7 由 Intel 與 EPM7096LC68-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7096LC68-7 | EPM7096LC68-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (EEPROM-based) | — |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | 52 |
| 封裝 | 68-pin J-Lead PLCC (LC68) | PLCC-68 (LC68) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | 4.75 V to 5.25 V (5 V nominal) |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | Yes (IEEE 1149.1 JTAG) |
| 工作溫度 | -40C to +85C (industrial, typical) | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| Architecture | EEPROM, second-generation MAX | — |
| Global Clock Pins | 6 | — |
| RoHS 狀態 | Non-compliant (legacy 5V PLCC) | — |
| Process Technology | CMOS EEPROM | — |
| Propagation Delay (tPD) | — | 15 ns |
| Programmable Technology | — | EEPROM (second-generation MAX architecture) |
| Logic Gates (typical) | — | 1800 gates |
| Memory Bits | — | Non-volatile configuration, 100 erase/program cycles per macrocell |
| Lead-Free / RoHS | — | Compliant per Altera product page |
| Programming Tool Support | — | Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV |