EPM7096LI68-15 vs EPM7096LC84-10 比較
詳細並排比較 EPM7096LI68-15 由 Intel 與 EPM7096LC84-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7096LI68-15 | EPM7096LC84-10 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | MAX 7000 (second-generation MAX architecture) | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 52 | — |
| Propagation Delay (tPD) | 15 ns | 10 ns (-10 speed grade) |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Programmable Logic Type | EEPROM-based, in-system programmable (ISP) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Boundary-Scan Test (BST) | Built-in JTAG BST circuitry | — |
| Output Option | Open-drain output option available | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| 封裝 | 68-pin PLCC (J-lead, QCCJ) | 84-PLCC (J-Lead) |
| 安裝類型 | Surface Mount (J-lead) | Surface Mount (PLCC socket or SMT) |
| Speed Grade | -15 (15 ns tPD) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Process Technology | CMOS EEPROM | EEPROM-based, 5.0 V low-power CMOS (L) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 36 |
| Supply Voltage (VCC) | — | 5.0 V nominal (4.75 V - 5.25 V) |
| In-System Programmability | — | Yes, via IEEE 1149.1 JTAG |
| MultiVolt I/O | — | 2.5 V / 3.3 V / 5.0 V mixed-voltage interface |
| 工作溫度範圍 | — | 0C to +70C (Commercial, 'C') |
| Configuration Memory | — | Non-volatile EEPROM (instant-on) |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |