EPM7096QI100-15 vs EPM7128EQI100-15 比較
詳細並排比較 EPM7096QI100-15 由 Altera 與 EPM7128EQI100-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128EQI100-15 - MAX 7000 CPLD, 128 Macrocells, 15ns | Altera/Intel
EPM7128EQI100-15 Obsolete規格比較
| 參數 | EPM7096QI100-15 | EPM7128EQI100-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 7000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | — |
| Number of Macrocells | 96 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 1,800 | — |
| Number of I/O Pins | 76 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| 工作溫度 | -40C to +85C (industrial, per Q-suffix) | -40 °C to +85 °C (industrial grade, "I" suffix) |
| 封裝 / 外殼 | 100-BQFP (BQFP-100) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Packaging | Tray | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status not stated in verified data] | Compliant (lead-free; verify per lot) |
| Family | — | MAX 7000 |
| Macrocells | — | 128 |
| Usable Gates | — | 2.5K |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| User I/O Pins | — | 84 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 4.75 V to 5.25 V (5 V nominal) |
| 封裝 | — | 100-pin PQFP (BQFP, 14x20 mm) |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Manufacturer | — | Altera (now Intel FPGA) |