EPM7128EQI100-15 vs EPM7128EQC100-20 比較
詳細並排比較 EPM7128EQI100-15 由 Altera 與 EPM7128EQC100-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128EQI100-15 - MAX 7000 CPLD, 128 Macrocells, 15ns | Altera/Intel
EPM7128EQI100-15 Obsolete規格比較
| 參數 | EPM7128EQI100-15 | EPM7128EQC100-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | EPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2.5K | 2.5K |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | — |
| User I/O Pins | 84 | — |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | -40 °C to +85 °C (industrial grade, "I" suffix) | 0 C to 90 C (Commercial) |
| 封裝 | 100-pin PQFP (BQFP, 14x20 mm) | 100-pin PQFP (BQFP, gull-wing) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | — |
| Boundary Scan | IEEE 1149.1 (JTAG) compliant | — |
| RoHS 狀態 | Compliant (lead-free; verify per lot) | — |
| Manufacturer | Altera (now Intel FPGA) | — |
| User I/Os | — | 84 |
| Logic Elements / LABs | — | 8 LABs (16 macrocells per LAB) |
| Propagation Delay (tpd) | — | 20 ns |
| Maximum Internal Frequency | — | 250 MHz |
| Technology | — | CMOS, UV-erasable / EEPROM |
| 供應電壓 | — | 5 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Compliance | — | RoHS compliance status not confirmed in web data |