EPM7128SQC100-10N vs EPM7128SQC100-10F 比較
詳細並排比較 EPM7128SQC100-10N 由 Altera 與 EPM7128SQC100-10F 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
EPM7128SQC100-10F ✓ 啟用中規格比較
| 參數 | EPM7128SQC100-10N | EPM7128SQC100-10F |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | 8 |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | 5 V |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| 封裝 | 100-pin PQFP (BQFP) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| 工作溫度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 100 MHz |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Lead-Free (F suffix) | — | Yes (Pb-free finish) |
| RoHS 狀態 | — | Compliant (F suffix variant) |