EPM7128SQC160-15 vs EPM7128SQC160-10 比較
詳細並排比較 EPM7128SQC160-15 由 Intel 與 EPM7128SQC160-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128SQC160-10 - MAX 7000 CPLD, 128 Cells, 100 I/O, 10ns | Altera
EPM7128SQC160-10 Obsolete規格比較
| 參數 | EPM7128SQC160-15 | EPM7128SQC160-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 7000 | MAX 7000S |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Number of Macrocells | 128 | — |
| Number of Logic Elements/Blocks | 8 (LABs of 16 macrocells each) | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 100 | — |
| Propagation Delay (tpd) | 15 ns max | — |
| Logic Element Propagation Delay | 4.5 ns | — |
| Maximum Operating Frequency | 125 MHz (internal feedback) | 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Logic Family | CMOS | — |
| 工作溫度 | 0C to +70C (commercial grade) | 0C to +70C (commercial) |
| 封裝 / 外殼 | 160-BQFP (160-PQFP, 28x28 mm) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | JTAG (IEEE 1149.1) / ByteBlaster |
| Configuration Memory | EEPROM (non-volatile, ~100 erase/program cycles) | Non-volatile EEPROM |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | — |
| Product Status | Obsolete (per distributor listings) | — |
| Family | — | MAX 7000 |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| User I/O Pins | — | 100 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5 V |
| 封裝 | — | 160-pin PQFP |
| Lead Pitch | — | 0.65 mm |
| Compliance | — | RoHS - see notes |