EPM7128SQI100-10 vs EPM7128SQC100-7 比較
詳細並排比較 EPM7128SQI100-10 由 Altera 與 EPM7128SQC100-7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoleteIntel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 Obsolete規格比較
| 參數 | EPM7128SQI100-10 | EPM7128SQC100-7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | 84 |
| Usable Gates | 2,500 | 2,500 |
| Logic Blocks (LABs) | 8 (16 macrocells each) | — |
| Package Type | PQFP-100 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 125 MHz to 250 MHz | 125 MHz |
| Counter Speed | Up to 175.4 MHz | — |
| Operating Voltage (VCC) | 5 V | — |
| 工作溫度 | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | — |
| Program/Erase Cycles | 100 minimum | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Logic Family | CMOS | — |
| I/O Compatibility | TTL-compatible, 5V/3.3V multi-voltage | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not in provided data] | Non-RoHS (legacy SnPb package) |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| Logic Elements / LABs | — | 4 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS, EEPROM-based, non-volatile |
| 封裝 | — | 100-pin PQFP (Plastic Quad Flat Pack) |
| Programming Interface | — | JTAG (IEEE Std 1149.1), in-system programmable |
| 安裝類型 | — | Surface Mount |