EPM7128STC100-10 vs EPM7160STC100-10F 比較
詳細並排比較 EPM7128STC100-10 由 Altera 與 EPM7160STC100-10F 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 Obsolete規格比較
| 參數 | EPM7128STC100-10 | EPM7160STC100-10F |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 3,200 |
| User I/Os | 84 | — |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | 5.0 V |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| 封裝 | TQFP-100 (C100) | 100-pin TQFP (1.0 mm height, lead-free) |
| 腳位數 | 100 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| 工作溫度 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status not in provided data] | Lead-free (suffix F indicates Pb-free) |
| Macrocells | — | 160 |
| Maximum User I/O Pins | — | 84 |
| Dedicated Inputs | — | 4 |
| Maximum Frequency (fMAX) | — | 100 MHz |
| Process Technology | — | CMOS, EEPROM-based |