EPM7160EQC100-20 vs EPM7128EQC100-20 比較

詳細並排比較 EPM7160EQC100-20 由 Altera 與 EPM7128EQC100-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM7160EQC100-20 EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 ⚠ 最後購買機會

規格比較

參數 EPM7160EQC100-20 EPM7128EQC100-20
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 NRND
Series MAX 7000 —
Family MAX 7000 CPLD MAX 7000
Architecture CMOS EEPROM-based, non-volatile —
Usable Gates 3,200 2.5K
Macrocells 160 128
Logic Array Blocks (LABs) 10 —
Maximum User I/Os 84 —
Pin-to-Pin Propagation Delay (tPD) 20 ns —
Maximum Internal Frequency (fCNT) 62.5 MHz —
Supply Voltage (VCCINT) 5 V nominal (4.75 V to 5.25 V) —
I/O Voltage Support 3.3 V or 5 V configurable —
封裝 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) 100-pin PQFP (BQFP, gull-wing)
安裝類型 Surface Mount Surface Mount
工作溫度 0 °C to +90 °C (commercial) 0 C to 90 C (Commercial)
In-System Programmability Yes (IEEE 1149.1 JTAG, 4-pin) —
Reprogram Cycles (typical) 100 —
RoHS 狀態 Not RoHS compliant (legacy Altera MAX 7000) —
Logic Elements per Macrocell 36 product terms (expandable) —
Device Type — EPLD (Complex Programmable Logic Device)
User I/Os — 84
Logic Elements / LABs — 8 LABs (16 macrocells per LAB)
Propagation Delay (tpd) — 20 ns
Maximum Internal Frequency — 250 MHz
Technology — CMOS, UV-erasable / EEPROM
供應電壓 — 5 V
In-System Programming — Yes (IEEE 1149.1 JTAG)
Compliance — RoHS compliance status not confirmed in web data

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