EPM7160EQC100-20 vs EPM7160ELC84-15 比較
詳細並排比較 EPM7160EQC100-20 由 Altera 與 EPM7160ELC84-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160EQC100-20 | EPM7160ELC84-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 7000 | — |
| Family | MAX 7000 CPLD | MAX 7000 |
| Architecture | CMOS EEPROM-based, non-volatile | EEPROM-based, second-generation MAX |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 10 | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Maximum Internal Frequency (fCNT) | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.75 V to 5.25 V) | — |
| I/O Voltage Support | 3.3 V or 5 V configurable | — |
| 封裝 | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| 工作溫度 | 0 °C to +90 °C (commercial) | 0 C to +70 C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 4-pin) | Yes (IEEE 1149.1 JTAG) |
| Reprogram Cycles (typical) | 100 | — |
| RoHS 狀態 | Not RoHS compliant (legacy Altera MAX 7000) | Contains lead / RoHS non-compliant (per Altera listing) |
| Logic Elements per Macrocell | 36 product terms (expandable) | — |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| Logic Array Blocks | — | 4 |
| Maximum I/O Pins | — | 36 |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Frequency | — | 76.9 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Package Type | — | 84-pin PLCC (J-Lead) |