EPM7160EQC100-20 vs EPM7160ELI84-20 比較
詳細並排比較 EPM7160EQC100-20 由 Altera 與 EPM7160ELI84-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160EQC100-20 | EPM7160ELI84-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 7000 | MAX 7000 |
| Family | MAX 7000 CPLD | — |
| Architecture | CMOS EEPROM-based, non-volatile | — |
| Usable Gates | 3,200 | 3.2K |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | 20 ns (speed grade '-20') |
| Maximum Internal Frequency (fCNT) | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.75 V to 5.25 V) | — |
| I/O Voltage Support | 3.3 V or 5 V configurable | — |
| 封裝 | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) | 84-Pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 °C to +90 °C (commercial) | -40C to +85C (Industrial grade 'I') |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 4-pin) | Yes (IEEE 1149.1 JTAG) |
| Reprogram Cycles (typical) | 100 | — |
| RoHS 狀態 | Not RoHS compliant (legacy Altera MAX 7000) | Not Compliant (per Arrow listing) |
| Logic Elements per Macrocell | 36 product terms (expandable) | — |
| Device Family | — | MAX 7000 (Complex Programmable Logic Device) |
| Number of Macrocells | — | 160 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Process Technology | — | CMOS, EEPROM-based configuration |
| Programmable Security | — | Yes (security bit) |
| Configuration Memory | — | Non-volatile EEPROM (instant-on) |