EPM7160SLC84-10N vs EPM7160ELC84-20 比較

詳細並排比較 EPM7160SLC84-10N 由 Intel 與 EPM7160ELC84-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM7160SLC84-10N EPM7160ELC84-20
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 7000S MAX 7000
Logic Elements / Macrocells 160 macrocells —
Usable Gates 3,200 gates 3,200
Logic Array Blocks (LABs) 4 —
User I/O Pins 64 (also reported as 60 or 36 depending on variant) 64
Pin-to-Pin Delay (tPD) 10 ns 20 ns
Counter Speed (fCNT) up to 175.4 MHz —
Maximum Operating Frequency 100 MHz —
Supply Voltage - Core (VCC) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programming Yes, via IEEE Std. 1149.1 JTAG —
Program / Erase Cycles 100 minimum —
Data Retention 20 years minimum —
封裝 84-pin PLCC (J-lead, surface mount) PLCC-84 (windowed ceramic carrier not applicable - plastic)
Operating Temperature Grade Commercial (0C to +70C) —
Lead-Free / RoHS Yes (-N suffix indicates lead-free) —
安裝類型 Surface Mount Surface Mount (PLCC socket compatible)
Macrocells — 160
Logic Array Blocks — 4
Supply Voltage (VCC) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Programming Interface — IEEE 1149.1 JTAG (ISP)
In-System Programmable — Yes (5.0-V ISP)
Technology — CMOS EEPROM
Architecture — Second-generation MAX
RoHS 狀態 — [DATA_NEEDED: RoHS compliance per specific part marking]
Global Clock Inputs — 4
Logic Element Type — EEPROM-based macrocell

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